The present invention generally relates to high performance testers for memory hierarchy cards and, more particularly, to such testers capable of running at speeds of the order of 100 MH.sub.Z using only off-the-shelf commercially available component parts.
Current high performance computer system memories are being architected in increasingly sophisticated manners. Logic is being included for fault alignment exclusion and for sparing techniques designed to make the memories more fault tolerant. Additionally, there is hierarchical circuit structure within the memory subsystem itself. Thus, the memory system includes substantial logic as well as memory on a card that must be tested together, thus necessitating a high speed digitized pulse generator providing large pulse widths for the slower portions of the hierarchical memory along with much narrower pulse widths for the faster memory portion.
More particularly, there are effectively three memories in a typical card-mounted multi-level memory, i.e., a high speed static write memory, a high speed static read memory and a dynamic array memory which is about an order of magnitude slower than the other two memories. On a Write command, the entire contents of the write memory is written broadside into the address specified in the array memory. On a Read command, the contents of the array memory at the address specified is read out broadside into the read memory. During the fast memory cycles, the write memory is loaded and the read memory is read out at memory cycle speeds of the order of 100 MH.sub.Z.
The relative speed difference of an order of magnitude between the slow and fast memory cycles, the unrestricted overlap of the Read and Write cycles of the static fast arrays and the somewhat restricted overlap with the slower array memory cause testing problems. Presently available test equipment is not fast enough and is architecturally incompatible with hierarchical memory testing in that the relationship is interlocked among generated cycle, timing edges and data which impedes the generation of simultaneously and overlapped control pulses and data for the faster and slower memories.
Attempts have been made to modify existing slow testers by adding a high performance adapted to interface with the memory to be tested. A typical approach is to run the slower tester at a submultiple of the faster static arrays and to design the adapter to fill in the time gaps. Such a technique suffers the following penalties: (1) It is costly and development time is long. (2) The modified tester is tailored to a specific application and is seldom reusable elsewhere. (3) Compromises are resorted to in the desired testing functions. (4) Any changes in the memory interface during the development cycle of the product to be tested could cause a major change in the adapter design. (5) The development cost of the adapter approaches the cost of the tester as the performance gap between the tester and the memory cards continues to widen.
In order to reduce the time required to exchange information between the tester and the accessing nodes of the device under test, a single local memory has been proposed for each data channel in the tester. This enhances the speed with which a device may be tested in that the various data channels can be operated simultaneously rather than sequentially by virtue of their local memory, as discussed in U.S. Pat. No. 4,433,414, issued Feb. 21, 1984 to M. E. Carey.
U.S. Pat. No. 4,287,594, issued Sept. 1, 1981 shows the use of two local memories in a single data channel tester for testing an integrated circuit. The two memories are read out simultaneously into associated temporary storage shift registers. The storage registers are accessed in alternation by a multiplexer which receives data in parallel from each shift register and converts it into serial form. Due to the simultaneous data entry into the temporary storage registers, it is necessary to wait for the settling of transients in each data entry cycle before the stored data is accessed by the multiplexer which causes wasteful delay in each operating cycle.
U.S. Pat. No. 4,451,918, issued May 29, 1984 to G. C. Gillette, further shows the use of two local memories in a single data channel tester in which the local memories are loaded with data in an interleaved fashion, i.e., one memory provides test data to the device under test while the other memory is loaded with new data from a selected one of back-up memories. In this way, continuous delivery at high rates of long sequences of test signals is provided to the device under test without requiring pauses to relaod the local memories. However, the single data channel is multiplexed among the device pins and no provision is made for providing output data pulses of variable pulse widths at high repetition rates.